PSO优化多核RVM的模拟电路故障预测

针对模拟电路健康管理的特点，提出了一种基于PSO优化多核RVM的模拟电路故障预测方法。利用参数分析得到电路的输出频域响应作为特征，计算其与电路无故障标准响应的欧氏距离来表征电路元件健康值，将多个核函数线性组合，并用PSO优化多核RVM参数后的模型实现对各个时间点元件的健康值变化轨迹进行预测。仿真结果表明，该方法在小样本情况下，预测效果优于单一核函数的RVM模型，适用于健康管理中实时预测，具有较好的实用性。     

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day.     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

A new realization scheme for dynamic PFSCL style

In this paper, a new scheme of logic function realization in dynamic positive feedback source-coupled logic (D-PFSCL) style is proposed. The existing scheme implements only NOR/OR based realization of a logic function. Thus, a complex function in D-PFSCL has high gate count which degrades the overall circuit performance measured in terms of power and delay. This paper therefore aims to resolve the issue by proposing a scheme which modifies the structure of a D-PFSCL gate. The modified gate exhibits AND/OR functionality and is used to realize various functions. Simulations have been carried out by implementing various functions and comparing their performance with the existing schemes at 1 GHz. The results of performance comparison with existing schemes indicates significant reuduction in gate count resulting in overall performance improvement.     

A Global Maximum Error Controller Based Nonlinearity Aware TPWL Method for Reducing Nonlinear Systems

Abstract

Model order reduction is a common practice to reduce large order systems so that their simulation and control become easy. Nonlinearity aware trajectory piecewise linear is a variation of trajectory piecewise linearization technique of order reduction that is used to reduce nonlinear systems. With this scheme, the reduced approximation of the system is generated by weighted sum of the linearized and reduced sub-models obtained at certain linearization points on the system trajectory. This scheme uses dynamically inspired weight assignment that makes the approximation nonlinearity aware. Just as weight assignment, the process of linearization points selection is also important for generating faithful approximations. This article uses a global maximum error controller based linearization points selection scheme according to which a state is chosen as a linearization point if the error between a current reduced model and the full order nonlinear system reaches a maximum value. A combination that not only selects linearization points based on an error controller but also assigns dynamic inspired weights is shown in this article. The proposed scheme generates approximations with higher accuracies. This is demonstrated by applying the proposed method to some benchmark nonlinear circuits including RC ladder network and inverter chain circuit and comparing the results with the conventional schemes.     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Quantum effect of cooling down the environment temperature of mesoscopic LC circuit

We examine the quantum effect of cooling down the environment temperature of mesoscopic LC circuit, and find that the ground state of the circuit is no longer in the thermo vacuum state, but in a negative binomial state. We calculate energy of the circuit in this new state, which increases with the cooling of the environment.     

有"石"之用--湖南大学法学院·建筑系馆群体设计

本文介绍了在湖南大学法学院、建筑系馆群体设计中,针对二者功能和空间上的不同需要,设计者从群体建筑的构成原则出发,重在体现法学院的内在逻辑性和建筑系馆空间的流动性;同时使用湘江砂石,运用水刷石工艺,对现代建筑设计中如何结合地域性进行了有益地探索.     

形式的逻辑──从提契诺学派看欧洲现代建筑

瑞士的提契诺学派以他们精练而娴熟的逻辑语言成为现代建筑的基本原理与地方文化结合的典范。以此为对象，尝试利用计算机技术对现代建筑作了本质性而非符号性的研究和分析。     

Full range analog Wheatstone bridge‐based automatic circuit for differential capacitance sensor evaluation

In this paper, an integrable novel fully analog Wheatstone bridge‐based interface for differential capacitance estimation is presented. Its working principle takes advantage of the modified De‐Sauty AC bridge configuration being employed only by two capacitors and two resistors. A feedback loop controls one of the resistors (e.g. a voltage‐controlled resistor), to obtain an evaluation of the differential capacitance variation on a full range, thanks to a general but very simple formula that considers both the ‘auto‐balancing’ and the bridge ‘out‐of‐equilibrium’ ranges. The proposed interface shows a satisfactory accuracy, being the percentage relative error within 0.45% for the experimental results. Copyright © 2016 John Wiley & Sons, Ltd.